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general description the max14500?ax14503 usb-to-sd card readers provide a means for portable devices that support full- speed usb communication (12mbps) with one or two sd card slots, upgrading the usb sd card reader func- tion to usb hi-speed (480mbps) operation. the max14500?ax14503 have two modes of operation: pass thru and card reader. in pass thru, the sd and usb signals pass through the max14500?ax14503 without modification, appearing like the device is not present. the host microprocessor firmware does not need modification, as there is no change from the host microprocessor? perspective. in card reader mode, the max14500?ax14503 implement a hi-speed usb card reader that operates independently of the host microprocessor. all the capabilities of the full-speed usb port and sd card slot are preserved with the addi- tional feature that allows a faster way for a pc to read or write to the sd card. the max14500?ax14503 sup- port sd high capacity sdhc cards. the 40-pin tqfn version supports one sd card, while the 56-bump wlp version supports two sd cards. the max14500?ax14503 feature advanced power- saving modes to reduce power consumption in portable applications. the low-power sleep modes allow the ability to disable internal circuit blocks, pro- viding power-saving operating modes. the default clock input for each part number is specified in the ordering information. the max14500?ax14503 fea- ture the option to change the default values using the i 2 c interface. the max14500?ax14503 are available in 5mm x 5mm, 40-pin tqfn, and 3.23mm x 3.5mm, 56-bump wlp packages. these devices operate over a wide supply voltage range and are specified over the -40? to +85? extended temperature range. features ? usb 2.0 hi-speed and full-speed compliant ? sdhc card support ? internal hi-speed usb sd card reader eases host ? overhead ? on-chip termination and pullup resistors ? internal sd switches allow for multiplexing two sd cards on a single-microprocessor sd port ? accommodates clock input frequencies 26mhz, 19.2mhz, 13mhz, and 12mhz ? internal clock squarer for low-amplitude tcxo signals ? no power-supply sequencing required ? compatible with +1.8v to +3.3v i/o host microprocessor ? simple control mode requires only a single gpio ? i 2 c control provides multiple configuration options ? i 2 c control required for two sd cards ? on-chip power-on reset/brown-out reset max14500?ax14503 hi-speed usb-to-sd card readers with bypass ________________________________________________________________ maxim integrated products 1 ordering information/ selector guide 19-4117; rev 1; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part input frequency (mhz) sd cards pin- package max14500 etl+* 12 1 40 tqfn-ep** max14500aewn+* 12 2 56 wlp max14501 etl+* 13 1 40 tqfn-ep** max14501aewn+* 13 2 56 wlp max14502 aetl+ 19.2 1 40 tqfn-ep** max14502aewn+* 19.2 2 56 wlp max14503 etl+* 26 1 40 tqfn-ep** max14503aewn+* 26 2 56 wlp applications cell phones pdas mp3 players digital still cameras gps note: all devices are specified over the -40? to +85? oper- ating temperature range. + denotes a lead(pb)-free/rohs-compliant package. * future product? ontact factory for availability. ** ep = exposed pad. sd is a trademark of the sd card association.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 2 _______________________________________________________________________________________ electrical characteristics (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units dc characteristics pass thru 2.1 3.6 card reader active, f cclk_ 26mhz 2.1 3.6 v cc supply voltage v cc card reader active, f cclk_ > 26mhz 2.4 3.6 v pass thru 2.0 3.6 card reader active, f cclk_ 26mhz 2.0 3.6 v sd supply voltage v sd card reader active, f cclk_ > 26mhz 2.4 3.6 v logic interface supply voltage v io 1.5 3.6 v usb supply voltage v tm 2.91 3.4 v digital core ldo regulator output voltage v cldo c cldo = 1.0? 1.8 v pass thru 5 15 a v cc supply current i cc card reader active 35 50 ma pass thru 17 40 ? v sd supply current i sd card reader active 3 ma pass thru 2 10 a v io supply current i io card reader active 0.2 ma pass thru 13 50 ? v tm supply current i tm card reader active 25 ma v sd comparator threshold v sdct 1.0 1.5 1.9 v v tm comparator threshold v tmct 2.0 2.5 2.9 v mode, i2c_sel, add, rst input-voltage low v il 0.4 v absolute maximum ratings (all voltages referenced to gnd.) v cc ...........................................................................-0.3v to +4v v sd ...........................................................................-0.3v to +4v v io ............................................................................-0.3v to +4v v tm ...........................................................................-0.3v to +4v kvbus......................................................................-0.3v to +4v cldo........................................................................-0.3v to +2v cdat1_[3:0], hdat1_[3:0], ccmd1, hcmd1, cclk1, hclk1, ccrd_prst, hcrd_prst, cdat2_[3:0], hdat2_[3:0], ccmd2, hcmd2, cclk2, hclk2 .........-0.3v to (v sd + 0.3v) busy , berr /int, mode, scl, sda, i2c_sel, add, rst .................................................-0.3v to (v io + 0.3v) cd+, cd-, hd+, hd-, rref, fref ............-0.3v to (v tm + 0.3v) continuous power dissipation (t a = +70?) 40-pin tqfn (derate 35.7mw/? above +70?) ........2857mw junction-to-case thermal resistance ( jc ) (note 1) 40-pin tqfn ................................................................1.7?/w junction-to-ambient thermal resistance ( ja ) (note 1) 40-pin tqfn .................................................................28?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max14500?ax14503 hi-speed usb-to-sd card readers with bypass _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units mode, i2c_sel, add, rst input-voltage high v ih 2/3 x v io v busy , berr /int output-voltage low v ol i load = 1ma 0.4 v busy , berr /int output-voltage high v oh i load = -1ma v io - 0.4 v i2c_sel, add, rst input leakage current i il -1 +1 ? mode input resistance to gnd r mode 150 300 500 k fref full-swing input-voltage high v ih 1.3 v fref full-swing input-voltage low v il 0.4 v fref low-amplitude input- voltage low v il 200 mv fref input leakage current i ilf full-swing mode -10 +10 ? fref input resistance low-amplitude input mode 1 m ? kvbus comparator threshold v th 1.0 1.25 1.5 v kvbus comparator hysteresis v hys 20 mv kvbus comparator input impedance r in 10 m sda/scl input low voltage v il_i2c 0.3 x v io v sda/scl input high voltage v ih_i2c 0.7 x v io v v io > +2v, 3ma sink current 0 0.4 sda output logic-low v ol_i2c v io +2v, 3ma sink current 0 0.2 x v io v sda/scl input leakage current i in_i2c -10 +10 ? sd card interface on-resistance r on v test = 0 or v sd , i test = 10ma (note 3) 10 off-leakage current i ilsd v test = 0 or v sd (note 3) -1 +1 ? off-capacitance c sd_off (note 4) 5 pf on-capacitance c sd_on (note 5) 10 pf pullup resistance r pu ccmd1, ccmd2, cdat1_[3:0], cdat2_[3:0] 50 75 100 k output high voltage v oh i oh = -100? 0.75 x v sd v output low voltage v ol i ol = 100? 0.125 x v sd v electrical characteristics (continued) (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units v sd < 2.4v 0.8 x v sd input high voltage v ih v sd 2.4v 0.625 x v sd v v sd < 2.4v 0.2 x v sd input low voltage v il v sd 2.4v 0.25 x v sd v usb interface on-resistance r on v cd_ = 0 or v tm , switch closed 5 on-resistance flatness r onflat v cd_ = 0 to 3.3v, v tm = +3.3v 2 on-capacitance c on_usb switch closed, measured from cd+ and cd- 12 pf off-capacitance c off_usb switch open, measured from cd+, cd-, hd+, hd- 6pf ac characteristics (note 6) sd card clock timing (cclk_), default speed (figure 5a) clock low time t wl c l = 10pf 19 ns clock high time t wh c l = 10pf 19 ns clock rise time t tlh c l = 10pf 10 ns clock fall time t thl c l = 10pf 10 ns sd card clock timing (cclk_), hi-speed (figure 5b) clock low time t wl c l = 40pf 7 ns clock high time t wh c l = 40pf 7 ns clock rise time t tlh c l = 40pf 3 ns clock fall time t thl c l = 40pf 3 ns sd card command timing (ccmd1, ccmd2) (figure 5b) input setup time t isu 5ns input hold time t ih 2ns output delay time during data transfer mode t odly 14 ns output hold time t oh 2.5 ns i 2 c characteristics scl clock frequency f scl 400 khz sda, scl capacitance c io_i2c 5pf sda output fall time t of_i2c 250 ns hold time after repeated start t hd,sta 0.6 ? electrical characteristics (continued) (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units clock low period t low_i2c 1.3 ? clock high period t high_i2c 0.6 ? setup time for repeated start t su,sta 0.6 ? hold time for data t hd,dat 0 0.9 ? setup time for data t su,dat 100 ns sda/scl input fall time t f_i2c 300 ns sda/scl rise time t r_i2c 300 ns setup time for stop t su,sto 0.6 ? bus free time between stop and start t buf 1.3 ? electrical characteristics (continued) (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2) parameter symbol conditions min typ max units dc characteristics hi-speed squelch detection threshold (diff signal amplitude) v hssq (note 6) 100 150 mv hi-speed differential input signaling levels v il specified by hi-speed receive eye diagram hi-speed data signaling common-mode voltage range scm (note 6) -50 +500 mv hi-speed idle level v hsoi -10 +10 mv hi-speed data signaling high v hsoh 360 440 mv hi-speed data signaling low v hsol -10 +10 mv chirp j level (differential voltage) v chirpj 700 1100 mv chirp k level (differential voltage) v chirpk -900 -500 mv ter m i nati on v ol tag e ( hi-speed) v hsterm -10 +10 mv ac characteristics rise time t hsr (note 6) 500 ps fall time t hsf (note 6) 500 ps driver waveform requirements s p eci fi ed b y h i - s p eed tr ansm i t eye d i ag r am see the typical operating characteristics section driver-output resistance z hsdrv 40.5 49.5 source jitter total (including frequency tolerance) s p eci fi ed b y h i - s p eed tr ansm i t eye d i ag r am see the typical operating characteristics section usb hi-speed source electrical characteristics (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units dc characteristics se receiver input high v ih 2.0 v se receiver input low v il 0.8 v differential common-mode voltage v cm 0.8 2.0 v receiver differential input sensitivity v di 0.2 v transmitter high v oh r l = 15k connected to gnd 2.8 3.6 v transmitter low v ol r l = 1.5k connected to 3.3v 0 0.3 v transmitter output signal crossover voltage v crs (note 6) 1.3 2.0 v bus pullup resistor on upstream facing port (idle bus) r pui 0.900 1.25 1.575 k bus pullup resistor on upstream facing port (upstream port receiving) r pua 1.425 2.5 3.090 k input impedance z inp 300 k termination voltage for upstream facing port pullup (r pu ) v term v tm v ac characteristics rise time t fr 420ns fall time t ff 420ns differential rise and fall time matching t frfm (note 6) 90 111.11 % full-speed data rate t fdraths 11.994 12.030 mbps usb full-speed source electrical characteristics (v cc = +2.4v to +3.6v, v sd = +2.4v to +3.6v, v io = +1.5v to +3.6v, v tm = +2.91v to +3.4v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?.) (note 2) note 2: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 3: on-resistance is measured by applying voltage and current on the sd card interface (cclk1, ccmd1, cdat1_[3:0], cclk2, ccmd2, cdat2_[3:0]). note 4: off-capacitance measured with sd switch open (cclk1, hclk1, ccmd1, hcmd1, cdat1_[3:0], hdat1_[3:0], cclk2, hclk2, ccmd2, hcmd2, cdat2_[3:0], hdat2_[3:0]). note 5: on-capacitance measured on sd card side (cclk1, ccmd1, cdat1_[3:0], cclk2, ccmd2, cdat2_[3:0]). note 6: specifications guaranteed by design.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass _______________________________________________________________________________________ 7 hi-speed eye diagram for card reader mode max14500 toc01 unit time interval differential voltage 0 2 6 4 8 10 0.9 1.7 1.3 2.1 2.5 2.9 3.3 usb on-resistance vs. usb common voltage (vcd_) max14500 toc02 vcd_ common voltage (v) r on ( ) v tm = 3.3v 0 10 5 20 15 30 25 35 0 1.0 0.5 1.5 2.0 2.5 sd channel on-resistance vs. sd channel common voltage max14500 toc03 sd channel common voltage (v) sd channel on-resistance ( ) v sd = +3v 0 2 1 4 3 5 6 2.0 2.8 2.4 3.2 3.6 pass thru v cc supply current vs. supply voltage max14500 toc04 v cc supply voltage (v) supply current ( a) no clock 4 3 2 1 0 1.5 2.4 1.8 2.1 2.7 3.0 3.3 pass thru v io supply current vs. supply voltage max14500 toc05 v io supply voltage (v) supply current ( a) no clock 0 10 5 20 15 25 30 1.8 3.3 pass thru v sd supply current vs. supply voltage max14500 toc06 v sd supply voltage (v) supply current ( a) 2.4 2.1 2.7 3.0 no clock typical operating characteristics (v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?, unless otherwise noted.)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +3.3v, v io = +2.5v, v sd = +2.5v, v tm = +3.3v, t a = +25?, unless otherwise noted.) 0 -20 0.1 1 10 100 1000 pass thru usb channel frequency response -16 max14500 toc10 frequency (mhz) on-loss (db) -12 -8 -4 -6 -10 -14 -18 -2 0.1 1 10 100 1000 pass thru sd channel off-isolation max14500 toc11 frequency (mhz) off-isolation (db) 0 -80 -60 -40 -20 0 2 6 4 8 10 -40 10 -15 35 60 85 pass thru v cc supply current vs. temperature max14500 toc07 temperature ( c) supply current ( a) no clock 33 32 31 30 29 2.0 2.8 2.4 3.2 3.6 card reader v cc supply current vs. supply voltage max14500 toc08 v cc supply voltage (v) supply current (ma) device enumerated data rate = 0mbps 17 19 18 21 20 22 23 2.9 3.4 card reader v tm supply current vs. supply voltage max14500 toc009 v tm supply voltage (v) supply current (ma) 3.1 3.0 3.2 3.3 device enumerated data rate = 0mbps
max14500?ax14503 hi-speed usb-to-sd card readers with bypass _______________________________________________________________________________________ 9 pin description pin tqfn wlp name function inputs/outputs 1 c4 i2c_sel i 2 c select input. i2c_sel must be connected to v io or gnd at power-up. drive i2c_sel low to disable i 2 c control and drive i2c_sel high to enable i 2 c control. 2 a2 scl i 2 c serial-clock input. scl is +3.6v tolerant and the high threshold is set by v io . if the i 2 c interface is not used, connect scl to gnd. 3 b4 sda i 2 c serial-data i/o. sda is +3.6v tolerant and the high threshold is set by v io . if the i 2 c interface is not used, connect sda to gnd. 4 a3 add i 2 c address selection input. connect add to v io or gnd to select between two i 2 c slave addresses: (gnd = 1110 000xb and v io = 1110 001xb). 6b6 berr /int card reader error/interrupt output. berr /int becomes berr for simple control and int for i 2 c control. berr /int goes low to indicate an error in card reader mode during simple control and asserts for enabled interrupts during i 2 c control. 7a7 busy busy output. busy asserts low to indicate device is in card reader mode. 8 c6 mode card reader/pass thru mode select input. mode is only active during simple control. drive mode low to enable pass thru mode and drive mode high to enable card reader mode. for i 2 c control, mode must be connected to gnd. 9b7 rst reset input. drive rst low to reset the internal registers to default values and put all outputs in high impedance. connect rst to v io for normal operation. 25 e6 fref frequency input. fref is the clock input (12mhz/13mhz/19.2mhz/26mhz) for the internal logic and usb phy. fref can accept a square-wave or sine-wave clock. an internal clock squaring circuit can be enabled or disabled through i 2 c. in simple control, the internal clock squarer is enabled by default. 27 f5 rref reference resistor. connect a bias resistor 6.19k ?% from rref to gnd. usb interface 22 g7 cd+ usb analog switch/hi-speed usb transceiver. cd+ connects to d+ on the usb connector. 21 f7 cd- usb analog switch/hi-speed usb transceiver. cd- connects to d- on the usb connector. 20 g8 hd+ usb analog switch. hd+ connects to d+ on the host side. 19 f8 hd- usb analog switch. hd- connects to d- on the host side. 28 e5 kvbus usb bus power-supply detection input. connect a resistor-divider between usb vbus, kvbus, and gnd. sd card interface 13 c8 cdat1_0 sd card 1 data bus analog switch/card reader interface. cdat1_0 connects to dat0 on the sd card. 12 b8 cdat1_1 sd data card 1 bus analog switch/card reader interface. cdat1_1 connects to dat1 on the sd card. 11 c7 cdat1_2 sd data card 1 bus analog switch/card reader interface. cdat1_2 connects to dat2 on the sd card.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 10 ______________________________________________________________________________________ pin description (continued) pin tqfn wlp name function 10 a8 cdat1_3 sd card 1 data bus analog switch/card reader interface. cdat1_3 connects to dat3 on the sd card. 34 e2 ccmd1 sd card 1 command analog switch/card reader interface. ccmd1 connects to cmd on the sd card. 32 e3 cclk1 sd card 1 clock analog switch/card reader interface. cclk1 connects to clk on the sd card. 33 f1 ccrd_prst sd card 1 analog switch for card present detection. ccrd_prst is the card detection line to the sd socket. when in pass thru mode, ccrd_prst is connected to hcrd_prst. 17 d7 hdat1_0 sd card 1 data bus analog switch. hdat1_0 connects to dat0 on the sd port of the host ?. 16 d8 hdat1_1 sd card 1 data bus analog switch. hdat1_1 connects to dat1 on the sd port of the host ?. 15 d6 hdat1_2 sd card 1 data bus analog switch. hdat1_2 connects to dat2 on the sd port of the host ?. 14 d5 hdat1_3 sd card 1 data bus analog switch. hdat1_3 connects to dat3 on the sd port of the host ?. 31 g1 hcmd1 sd card 1 command analog switch. hcmd1 connects to cmd on the sd port of the host ?. 29 g2 hclk1 s d c ar d 1 c l ock anal og s w i tch. h c lk1 connects to c lk on the s d p or t of the host ? . 30 f2 hcrd_prst sd card 1 analog switch for card present detection. hcrd_prst is connected to ccrd_prst in pass thru mode. d2 cdat2_0 sd card 2 data bus analog switch/card reader interface. cdat2_0 connects to dat0 on the sd card. d1 cdat2_1 sd card 2 data bus analog switch/card reader interface. cdat2_1 connects to dat1 on the sd card. b5 cdat2_2 sd card 2 data bus analog switch/card reader interface. cdat2_2 connects to dat2 on the sd card. a5 cdat2_3 sd card 2 data bus analog switch/card reader interface. cdat2_3 connects to dat3 on the sd card. f4 ccmd2 sd card 2 command analog switch/card reader interface. ccmd2 connects to cmd on the sd card. f3 cclk2 sd card 2 clock analog switch/card reader interface. cclk2 connects to clk on the sd card. d3 hdat2_0 sd card 2 data bus analog switch. hdat2_0 connects to dat0 on the sd port of the host ?. e1 hdat2_1 sd card 2 data bus analog switch. hdat2_1 connects to dat1 on the sd port of the host ?.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 11 pin description (continued) pin tqfn wlp name function c5 hdat2_2 sd card 2 data bus analog switch. hdat2_2 connects to dat2 on the sd port of the host ?. a4 hdat2_3 sd card 2 data bus analog switch. hdat2_3 connects to dat3 on the sd port of the host ?. g4 hcmd2 sd card 2 command analog switch. hcmd2 connects to cmd on the sd port of the host ?. g3 hclk2 s d c ar d 2 c l ock anal og s w i tch. h c lk2 connects to c lk on the s d p or t of the host ? . power supply 5a6v io i/o logic-level translator voltage. bypass v io to gnd with a 0.1? ceramic capacitor. v io powers the logic inputs/outputs and i 2 c block. 23 f6 v tm usb analog switch and transceiver power supply. bypass v tm to gnd with a 0.1? ceramic capacitor. 38 b1, b2 cldo bypass capacitor for internal +1.8v ldo. connect a 1? ceramic capacitor (x7r, x5r, or better) from cldo to gnd. cldo must not be used to power external circuitry. 39 b3, c3 v cc digital supply voltage. bypass v cc to gnd with a 1? ceramic capacitor (x7r, x5r, or better). 40 a1 v sd sd card voltage. bypass v sd to gnd with a 1? ceramic capacitor (x7r, x5r, or better). 18, 24, 26, 37 c1, c2, e7, e8, g5, g6 gnd ground no connection 35, 36 d4, e4 n.c. no connection. connect n.c. to gnd. exposed pad ep exposed pad. connect ep to gnd. do not use ep as the sole gnd connection.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 12 ______________________________________________________________________________________ usb usb connector d+ d- sd slot simple control v io fref vbus sd card interface v sd v cc mode i2c_sel add sda scl usb hs card reader v sd 4 4 gnd hcrd_prst hclk1 hcmd1 hdat1_[3:0] ccrd_prst cclk1 ccmd1 cdat1_[3:0] cldo kvbus cd+ cd- hd+ hd- usb transceiver v cc berr busy v tm usb switches v tm sd port 1 switches rref i/o level transla tors v io host i/o host processor sd port max14500? max14503 figure 1. typical application circuit for simple control mode with one sd card
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 13 usb connector d+ d- sd slot v io fref vbus sd card interface v sd v cc mode i2c_sel add sda scl usb hs card reader v sd 4 4 gnd hcrd_prst hclk1 hcmd1 hdat1_[3:0] ccrd_prst cclk1 ccmd1 cdat1_[3:0] cldo kvbus cd+ cd- hd+ hd- usb transceiver v cc int busy v tm usb switches v tm sd port 1 switches rref i/o level transla tors v io host i/o host processor sd port optional v io usb max14500? max14503 i 2 c control figure 2. typical application circuit for i 2 c control mode with one sd card
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 14 ______________________________________________________________________________________ usb connector d+ d- vbus gnd usb host i/o host processor sd port1 v io v tm sd slot1 fref sd card interface v sd v cc mode int i2c_sel sda scl usb hs card reader 4 4 hcrd_prst hclk1 hcmd1 hdat1_[3:0] ccrd_prst cclk1 ccmd1 cdat1_[3:0] cldo cd+ cd- hd+ hd- usb tranceiver sd slot2 4 hclk2 hcmd2 hdat2_[3:0] cclk2 ccmd2 cdat2_[3:0] busy v io add v io optional rref kvbus sd port 2 switches sd port 1 switches v cc v sd i/o level transla tors v tm usb switches sd port2 4 max14500? max14503 i 2 c control figure 3. typical application circuit for i 2 c control mode with two sd cards
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 15 usb connector d+ d- vbus gnd usb host i/o host processor sd port v io v tm sd slot1 fref sd card interface v sd v cc mode int i2c_sel sda scl usb hs card reader 4 4 hcrd_prst hclk1 hcmd1 hdat1_[3:0] ccrd_prst cclk1 ccmd1 cdat1_[3:0] cldo cd+ cd- hd+ hd- usb tranceiver sd slot2 4 hclk2 hcmd2 hdat2_[3:0] cclk2 ccmd2 cdat2_[3:0] busy v io add v io optional rref kvbus sd port 2 switches sd port 1 switches v cc v sd i/o level transla tors v tm usb switches max14500? max14503 i 2 c control figure 4. typical application circuit for i 2 c control mode with one sd port and two sd cards
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 16 ______________________________________________________________________________________ f pp t wl t wh t tlh t ih t odly (min) shaded areas are not valid t thl t isu t odly (max) v ih v il v ih v il v oh v ol clock input output figure 5a. sd card default timing diagram timing diagrams
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 17 f pp t wl t wh t tlh t ih t thl t isu t odly t oh v ih v il v ih v il v oh v ol cclk1 cclk2 cdat1 _[3:0], cdat2_[3:0], ccmd1, ccmd2 (read) v oh cdat1 _[3:0], cdat2_[3:0], ccmd1, ccmd2 (write) v ih v il v ol figure 5b. sd card hi-speed timing diagram timing diagrams (continued)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 18 ______________________________________________________________________________________ detailed description the max14500?ax14503 can be added to devices that have an sd card slot and a usb full-speed port (12mbps) to provide a hi-speed usb path to an sd card bypassing the host microprocessor (?), allowing for faster sd card transfers (figures 1?). without the max14500?ax14503, a host ? with a full-speed usb port moves data between an sd card and a host pc at 12mbps when transferring data from an sd card through usb. the host ? has additional overhead because it has to accept data from the sd cards, process the data by putting it in usb format, and then transfer the data through the usb port. the max14500 max14503 create an alternate path from the sd card to usb, providing usb hi-speed capability. by bypassing the host ? using the max14500?ax14503, sd card read and write operations are not limited by host ? overhead and usb full-speed data rates. the max14500?ax14503 operate in pass thru and card reader mode. in pass thru mode, the max14500 max14503 are transparent to the host ?. all read and write operations pass from the host ? sd port to the sd card without modification. all of the features of the original device are intact and there is no need to change firmware in the host ?. in card reader mode, the sd card is con- nected to the pc with the internal usb hi-speed card reader, bypassing the host ?. the max14500?ax14503 can be controlled in two ways. the simple control method uses a single output from a ? or asic to select pass thru or card reader mode. only one sd card can be used as a hi-speed usb card reader in simple control. i 2 c control allows more configuration options and provides status informa- tion along with error conditions and additional interrupts. two sd cards can be connected and each set of sd port switches can be controlled independently (two sd port version under i 2 c control). the state of i2c_sel must not change after v io is applied. with i 2 c control, the i 2 c bus is used to read and write to internal registers for configuration, error checking, con- trol, and status reporting. the control and configuration registers have various functions including wakeup, sd card selection, interrupt enable, and sd switch settings. the status registers give the status of errors, sd card detection, power supplies, and interrupts. putting the max14500?ax14503 to sleep puts the device into pass thru mode. the state of sd port switches for card 1 and card 2 can be changed while in pass thru. some i 2 c commands are executed upon waking up or entering card reader mode. for register settings that involve card reader mode, (when in sleep mode), program- ming the i 2 c registers changes the values, but the actions do not execute until the internal logic wakes up or card reader mode is entered. the register map indi- cates when register bit changes take effect. sda scl t hd,sta t low_i2c t high_i2c t r_i2c t f_i2c t su,dat t su,sta t su,sto t buf t hd,sta t hd,dat start condition stop condition start condition repeated start condition t f_i2c t r_i2c figure 6. i 2 c timing diagram timing diagrams (continued)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 19 register name register address (hex) power-up value (hex) power-up default settings control register (control) 0x00 0x18 sd2sw = 1, sd switch 2 is closed sd1sw = 1, sd switch 1 is closed mode[1:0] = 00, card reader mode is not active wakeup = 0, shutdown configuration register 1 (config1) 0x01 0x00 sd2onebit = 0, sd2 bus in 4-bit data mode sd1onebit = 0, sd1 bus in 4-bit data mode intpulse = 0, int stays asserted until status register is read intacthi = 0, int asserts active low configuration register 2 (config2) 0x02 0x00 clksource = 00000, default clock input forcefs = 0, usb hi-speed configuration register 3 (config3) 0x03 0x00 sd2maxclk = 0000, default clock (base sd clock) sd1maxclk = 0000, default clock (base sd clock) interrupt enable register 1 (ie1) 0x04 0x00 usbfs = 0, disable int for full-speed status change usbsr = 0, disable int for suspend/resume status change vtm = 0, disable int for v tm status change vsd = 0, disable int for v sd status change kvbus = 0, disable int for vbus status change bsy = 0, disable int for busy status change sdstat = 0, disable int for sd card status change interrupt enable register 2 (ie2) 0x05 0x00 fwupd = 0, disable int for firmware update status change usb vendor id high byte (usbvidh) 0x06 0x00 if vid = 0x0000, 0x06ba is used during usb enumeration, vid high byte = 0x06 usb vendor id low byte (usbvidl) 0x07 0x00 if vid = 0x0000, 0x06ba is used during usb enumeration, vid low byte = 0xba usb product id high byte (usbpidh) 0x08 0x00 if pid = 0x0000, 0x38a4 is used during usb enumeration, pid high byte = 0x38 usb product id low byte (usbpidl) 0x09 0x00 if pid = 0x0000, 0x38a4 is used during usb enumeration. pid low byte = 0xa4 table 1. power-up default mini register map for configuration registers
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 20 ______________________________________________________________________________________ default power-up (pass thru mode) in the default pass thru mode, the max14500 max14503 are transparent and the existing host func- tions (access to sd cards and usb) are preserved (figure 7). the host ? reads and writes data to the sd card from the sd port, and can communicate to a pc through its existing full-speed usb port. all of the fea- tures of the original chipset are intact. the max14500 max14503 sleep when in pass thru mode (wakeup = 0), when the mode input is low, or when the mode bits [2:1] in control register (0x00) are set to card reader mode, not active. in sleep mode, the internal microcon- troller is turned off and current consumption is mini- mized. the settings for sd port switches for card 1 and card 2 are controlled by sd port switch bits [4:3] in the control register. card reader mode in card reader mode, the pc communicates with the sd card through usb with an internal hi-speed sd card reader, bypassing the host ?. figure 8 shows card reader mode with sd card 1 connected to the pc with the internal card reader. the 40-pin tqfn can connect to a single sd card in card reader mode. with the 56-bump wlp operating under i 2 c control, either sd card can be selected for card reader mode. cclk2 ccmd2 cdat2_[3:0] hclk2 hcmd2 hdat2_[3:0] 4 4 sd port2 sd slot2 cd+ sd port 2 switches host processor usb switches cd- d+ d- hd+ hd- usb usb connector sd card interface usb hs card reader ccrd_prst sd port 1 switches cclk1 ccmd1 hcrd_prst hclk1 hcmd1 4 4 cdat1_[3:0] hdat1_[3:0] sd port1 i/o level translators host i/o sd slot1 usb transceiver max14500? max14503 figure 7. default startup (pass thru mode)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 21 when the card reader is initiated in the control register, the internal usb switch disconnects from the host ? usb port and connects to the internal usb hi-speed sd card reader unit. when the max14500?ax14503 disconnect from the host to implement a stand-alone high-speed card reader, it simulates a disconnect on the host usb and sd ports to maintain data coherence. the sd connections are restored to the host ? by clos- ing the analog switch connecting ccrd_prst to hcrd_prst. certain registers execute actions when entering card reader mode. these actions are only valid for card reader mode. writing to these registers in sleep mode, or when awake, updates the registers, but the action is carried out when card reader mode is activated for one of the sd cards (see the register map section). when card reader mode is initially entered, the internal microcontroller enumerates with the pc to establish a high-speed usb mass storage device. no actions by the host ? are required for enumeration other than entering card reader mode. once the usb-sd card connection is established, pc to sd card data transfer begins and various interrupts monitor the status the of card reader mode if enabled. the bsy flag is represented externally by the busy output and can be read serially through i 2 c. the busy output is always active. if the host ? requests sleep mode in the middle of the data transfer, the max14500?ax14503 do not complete the transfer, exit card reader mode, reconnect usb switches, and cclk2 ccmd2 cdat2_[3:0] hclk2 hcmd2 hdat2_[3:0] 4 4 sd port2 sd slot2 cd+ sd port 2 switches host processor usb switches cd- d+ d- hd+ hd- usb usb connector sd card interface usb hs card reader ccrd_prst sd port 1 switches cclk1 ccmd1 hcrd_prst hclk1 hcmd1 4 4 cdat1_[3:0] hdat1_[3:0] sd port1 i/o level translators host i/o sd slot1 usb transceiver max14500? max14503 figure 8. card reader mode. the usb port is connected to sd card 1. in the 2 port version, a second sd card (sd slot 2) can be independently connected and disconnected to the host ?.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 22 ______________________________________________________________________________________ go to sleep. because the busy output (bsy bit in i 2 c) indicates card reader mode, the host ? may monitor this output after commanding a mode change to deter- mine when the change takes place (figure 9). if the host requests the other sd card to enter card reader mode, the busy flag deasserts and reasserts to let the host know that the change took place. simple control (i2c_sel = low) the max14500?ax14503 feature a very simple con- trol scheme for entering card reader mode that requires a single logic (gpio) from the host ?. the simple control may only be used with the single sd port versions. when i2c_sel is connected low at startup, the mode input controls whether the device is in pass thru or card reader mode. driving mode low enables pass thru mode (figure 10), and the host ? has a direct connection to the sd card and usb connector through internal analog switches. driving mode high enables card reader mode between sd card 1 and the pc through the usb connector (figure 11). berr /int functions as the bridge error output berr that asserts for card reader errors. interrupts are not enabled, the clock source is set to the default as defined by the part number, and the berr and busy outputs are active. upon mode transitioning high, sd card 1 connects to the usb connector in card reader mode and busy asserts low. the busy output indi- cates that the device is in card reader mode. busy may be important to the host ?, as the time to com- plete enumeration/de-enumeration may take a long time (> 100ms). i 2 c control (i2c_sel = high) the max14500?ax14503 feature i 2 c control that allows access to internal registers for complete control over configuration, sd port analog switches, interrupts, clock configuration, advanced power-on states, and error status. i 2 c control uses i 2 c to serially program the max14500?ax14503 to be in card reader or pass thru mode, and allows either sd card to be connected in card reader mode. while a sd card is connected in card reader mode, the other sd port analog switches can be independently controlled serially through i 2 c. using the i 2 c bus to put the device to sleep minimizes the supply current while maintaining control over the sd port switches. pass thru request to enter card reader request to sleep or pass thru if awake if asleep no sd command in progress sd command in progress ? disconnect sd switches for card reader ? enumerate sd card ? open usb switches card reader (transfer data) ? deenumerate pc ? close usb switches ? deenumerate sd card ? restore sd switches to i 2 c settings ? deassert busy ? clear busy flag ? assert busy ? set busy flag ? enumerate pc figure 9. card reader flow chart
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 23 control register (0x00) the control register controls the settings of sd port analog switches, card reader mode, and sleep (table 2.) the state of the sd port analog switches can be changed when the device is in sleep mode or in card reader mode, and actions are executed immediately. if sd card 1 is connected to the pc through usb in card reader mode, the state of the sd port 1 switches are ignored, but the sd port 2 switches can still be con- trolled through the control register. likewise, if sd card 2 is connected to the usb connector in card reader mode, the state of the sd port 2 switches are ignored, but the sd port 1 switches can still be controlled through the control register. changing the card reader bits in sleep mode does not cause the device to enter card reader mode. under this condition, the max14500?ax14503 enter card reader mode upon waking up. configuration registers the max14500?ax14503 have three configuration reg- isters (config1 = 0x01, config2 = 0x02, config3 = 0x03). the configuration registers control the sd bus bit data mode, interrupt polarity, interrupt clearance, clock configuration, sd clock, and usb speed for card reader mode. the default settings are shown in the register map section. interrupts (int) all interrupts are masked in the default reset state. there are two interrupt enable registers (ie1 = 0x04, ie2 = 0x05) and two interrupt request registers (irq1 = 0x10, irq2 = 0x11). the berr /int output functions as the bridge error output berr in simple control and func- tions as an interrupt int in i 2 c control. the polarity of int and how int is asserted can be programmed in config1. the int output asserts for enabled interrupts and errors in card reader mode. the polarity of int can be active-high or active-low, and int can be pro- hcrd_prst hclk1 hcmd1 hdat1_[3:0] cd+ host processor usb switches cd- d+ d- hd+ hd- usb usb connector sd card interface usb hs card reader ccrd_prst sd port 1 switches cclk1 ccmd1 busy berr mode = low 4 4 cdat1_[3:0] i2c_sel = low sd port1 i/o level translators host i/o sd slot 1 usb transceiver max14500? max14503 figure 10. i2c_sel connected low to enable simple control and mode = 0 to enable pass thru
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 24 ______________________________________________________________________________________ grammed to stay asserted until the status register is read, or stay asserted for 10ms. if int is programmed to stay asserted, a read to the status register is required to clear int. int can be programmed to be active-high or active-low when i2c_sel is high (i 2 c control). int is high impedance in sleep mode (wakeup = 0), regard- less of the int polarity programmed in the i 2 c registers. use a pullup or pulldown resistor for the desired inactive int polarity state during sleep mode. interrupt masking all interrupts are masked at power-up. while masked interrupts do not assert the int output, they do register as changes in the interrupt request registers (irq1 and irq2). the status register (status1 = 0x12) indicates the current state of the interrupt bits. if interrupts are masked, polling irq1 and irq2 indicate the fields with changes, and status1 gives the current state. reading the irq registers resets the interrupt request bits. if polling is used to read the device status, it is required to read both the status register and the inter- rupt request registers to check for state changes. usb interrupts when enabled, the int output asserts an interrupt for changes in the usb connection and if the operating system suspends the usb connection. vbus is detect- ed at the kvbus input and changes in vbus voltage can assert an interrupt when enabled. power-supply interrupts the max14500?ax14503 feature many advanced power-saving modes. v cc , v sd , and v tm do not need to be applied for i 2 c communication. changes in v sd and v tm can assert an interrupt when enabled to indicate dif- ferent power-saving modes (see the power-supply modes section). busy interrupt when enabled, changes in the bsy bit can assert an interrupt (see the busy indication (bsy) section). sd status interrupt when enabled, the sdstat bit asserts an interrupt for card detection and removal upon entering card reader mode for the sd card socket configured as the card reader. the sdstat bit is not active during pass thru mode and does not change states in the irq registers upon card insertion and removal during pass thru mode. bit description value function default [7:5] reserved 000 set these bits to 0. 000 0 analog switches are open, disconnecting the sd port from the sd card. 4 sd port 2 analog switches sd port 2 is a set of six analog switches connecting the sd port to the sd card. this set contains: clock (cclk2), command (ccmd2), and four data lines (cdat2_[3:0]). the card-present line is not available for this port. this setting is ignored when card reader mode is enabled for this port. 1 analog switches are closed, connecting the sd port to the sd card. 1 0 analog switches are open, disconnecting the sd port from the sd card. 3 sd port 1 analog switches sd port 1 is a set of seven analog switches connecting the sd port to the sd card. this set contains: card-present (ccrd_prst), clock (cclk1), command (ccmd1), and four data lines (cdat1_[3:0]). the difference between port 1 and port 2 is the card-present line. this setting is ignored when card reader mode is enabled for this port. 1 analog switches are closed, connecting the sd port to the sd card. 1 00, 11 card reader mode not active. 01 card reader mode active: connects to sd card 1. [2:1] card reader mode changing these bits in sleep mode does not execute the action until the host ? wakes up the max14500?ax14503. 10 card reader mode active: connects to sd card 2. 00 0 request internal logic to shut down. 0 wakeup in sleep mode, the max14500?ax14503 are in pass thru mode. sd port switches are controlled by their respective bits. entering sleep mode reduces the supply current by turning off the internal logic. request to shut down may be delayed due to usb and de- enumeration. 1 wake up internal logic. 0 table 2. control register (0x00)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 25 error checking in simple control, the berr /int output functions as berr and indicates if an error occurs during card reader mode. if berr asserts low to indicate an error, the max14500?ax14503 stay in card reader mode. if the error clears, data transfer begins. berr asserts if kvbus, v tm , or v sd are not present. it is recommend- ed that mode be pulled low when berr indicates an error to return the max14500?ax14503 to pass thru mode for the host ? to clear the error. in i 2 c control, berr /int functions as an interrupt out- put (int) and asserts for errors encountered in card reader mode when interrupts are not masked. to find the source of the interrupt, read the interrupt request registers and status register. busy indication (bsy) the busy output is used in simple control and i 2 c con- trol to indicate when card reader mode is active. in simple control, transitioning mode high to low requests the internal microcontroller to enable pass thru mode. busy asserts low while in card reader mode and deasserts high in pass thru mode. the bsy bit in status1 (0x12) behaves similarly with i 2 c control. the busy output is represented by the bsy bit. requests to put the device to sleep or bypass (pass thru mode) while in card reader mode can be verified by checking the state of the busy signal or bsy bit. the busy output indicates the status of the busy flag in status1. the bsy bit is 1 when the busy output asserts low. when enabled, changes in the busy flag cause an interrupt. in i 2 c control, either the bsy bit or the busy output give the status of the busy state. hcrd_prst hclk1 hcmd1 hdat1_[3:0] cd+ host processor usb switches cd- d+ d- hd+ hd- usb usb connector sd card interface usb hs card reader ccrd_prst sd port 1 switches cclk1 ccmd1 busy berr mode = high 4 4 cdat1_[3:0] i2c_sel = low sd port1 i/o level translators host i/o sd slot 1 usb transceiver max14500? max14503 figure 11. i2c_sel is connected low to enable simple control and mode = 1 to enable card reader mode for sd card 1.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 26 ______________________________________________________________________________________ reset ( rst ) drive rst low to reset all the registers to the default value and minimize the supply current. sleep the max14500?ax14503 can be put to sleep by pro- gramming the wakeup bit to 0 in the control register with i 2 c control, or by driving the mode input low in simple control. this turns off the internal microcontroller to minimize current. reads and writes to the i 2 c are still functional, and registers can be updated with new val- ues. most register actions do not take effect until the internal microcontroller wakes up or when card reader mode is enabled. the sd port analog switches can change states while the internal microcontroller is in sleep mode. the register map section shows which registers are enabled in sleep mode, at power-up, and upon entering card reader mode. clock configuration the max14500?ax14503 come preprogrammed to accept a 12mhz, 13mhz, 19.2mhz, or 26mhz default clock input with the clock squarer enabled for low- amplitude tcxo signals (see the ordering information/selector guide ). this clock is used for the usb and sd subsystems and is not required for opera- tion of the i 2 c interface. this allows the clock frequency to be changed in the system. the pll subsystem con- runtime note: this is valid for i 2 c control only interrupt request registers read? is int enabled? has interrupt status changed? is interrupt mask bit enabled? yes yes yes yes ? interrupt status register bit updated ? interrupt request register bit set clear int int enabled-based on intpulse and intacthi field settings interrupt activity occurs no no no no figure 12. typical interrupt servicing flowchart
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 27 sists of two blocks: a clock squarer input (enabled by default), which accepts low-signal amplitude tcxo sig- nals (down to 200mv), and a pll with fixed dividers. the pll sub system can be configured using the i 2 c interface. the complete list of pll subsystem combina- tions are listed in table 3. i 2 c serial interface serial addressing the max14500?ax14503 operate as i 2 c slave devices that send and receive data through an i 2 c-compatible 2-wire interface. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirec- tional communication between master(s) and slave(s). a master initiates all data transfers to and from the max14500?ax14503, and generates the scl clock that synchronizes the data transfer. the sda line oper- ates as both an input and an open-drain output requiring a pullup resistor on sda. the scl line operates only as an input. a pullup resistor is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start (s) condition by a master, followed by the max14500?ax14503? 7-bit slave address, plus a r/ w bit, a register address byte, one or more data bytes, and finally a stop (p) condition. start and stop conditions both scl and sda remain high when the interface is idle. a master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high (figure 13). when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. clksource source (mhz) notes 00000b see ordering information/ selector guide default low-amplitude clock 00001b 19.2 rail-to-rail square wave 00010b 19.2 low-amplitude sine wave 00101b 13.0 rail-to-rail square wave 00110b 13.0 low-amplitude sine wave 01001b 12.0 rail-to-rail square wave 01010b 12.0 low-amplitude sine wave 01101b 26.0 rail-to-rail square wave 01110b 26.0 low-amplitude sine wave table 3. clock source bit values sda scl start condition stop condition s p figure 13. start and stop conditions
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 28 ______________________________________________________________________________________ bit transfer one data bit is transferred during each clock pulse (figure 14). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit (figure 15), which the recipient uses to handshake receipt of each byte of data. each byte transferred effectively requires nine bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknow- ledge clock pulse. the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the max14500?ax14503, the max14500?ax14503 generate the acknowledge bit because the max14500?ax14503 are the recipients. when the max14500?ax14503 are transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave addresses the max14500?ax14503 have a 7-bit long slave address. the bit following the 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. the address bit add is externally driven high or low by the add input to select between two slave addresses to avoid conflict with other i 2 c addresses (figure 16). table 4 shows the binary values for reads and writes. scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s figure 15. acknowledge sda scl data line stable; data valid change of data allowed figure 14. bit transfer sda 1 ack scl msb lsb 1 0 r/w 1 0 0 add figure 16. slave address add function device address high read 11100011 high write 11100010 gnd read 11100001 gnd write 11100000 table 4. slave addresses
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 29 format for writing a write to the max14500?ax14503 comprises the transmission of the slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the register address or command byte. the register address determines which register of the max14500?ax14503 is to be written by the next byte if received. if a stop condition is detected after the register address is received, then the max14500 max14503 take no further action beyond storing the register address (figure 17). any bytes received after the register address are data bytes. the first data byte goes into the register selected by the register address and subsequent data bytes go into subsequent registers (figure 18). if multiple data bytes are transmitted before a stop condition, these bytes are stored in subsequent registers because the register address autoincrements. format for reading the max14500?ax14503 are read using the internal- ly stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules used for a write. thus, a read is initiated by first configuring the register address by performing a write (figure 19). the master can now read consecutive bytes from the max14500?ax14503, with the first data byte being read from the register addressed pointed by the previ- ously written register address (figure 20). once the master sends a nack, the max14500?ax14503 stop sending valid data. applications information sd ports the max14500?ax14503 support one or two sd cards or sd interface nand flash memory. sd ports configuration there are three operational configurations: 40-pin tqfn version, containing one host port and one sd card (figures 1, 2) 56-bump wlp version, containing two sd host ports and two sd cards. there are two sd hosts and two sd memory cards. use this mode if the host has two sd ports (figure 3). 1110 00 0 address = 0xe0 register 0x01 write data s d7 d6 d5 d4 d2 d1 d3 0 = write 0000 001 0 register address = 0x01 0a a p d0 a/a s = start bit p = stop bit a = ack a = nack d_ = data bit figure 17. format for i 2 c write. in this example the register 0x01 is written. 1110 00 0 address = 0xe0 register 0x01 write data s d7 d6 d5 d4 d2 d1 d3 0 = write 0000 001 0 register address = 0x01 0a a d0 a register 0x02 write data d7 d6 d5 d4 d2 d1 d3 p d0 a/a figure 18. format for writing to multiple registers. in this example, registers 0x01 and 0x02 are written in sequence.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 30 ______________________________________________________________________________________ 56-bump wlp version, containing one port and two sd cards. the host sd ports 1 and 2 are connected together at the host. this configuration allows two sd cards connected to one host, but only one sd card is connected to the host at a time. the host uses the max14500?ax14503? internal sd port switches to multiplex between the cards. this con- figuration can also be used to limit the bus capaci- tive loading of having two cards connected at the same time to the bus (figure 4). sd card clock frequency the sd card clock frequency is the lower of the maxi- mum the card can support as read from the sd card and base sd clock (base sd clock is determined from values shown in table 5). the max14500?ax14503 internally read the max frequency directly from the sd card. in i 2 c control, the maximum clock frequency is programmable to values lower than the maximum allowed by the sd card, helping with issues such as excessive bus capacitance causing data errors. 1110 00 0 address = 0xe0 s 0 = write 0000 001 0 register address = 0x01 0 1110 00 0 address = 0xe1 s 1 = read 1 a a register 0x01 read data d7 d6 d5 d4 d2 d1 d3 p d0 a/a p a figure 19. format for reading 1110 00 0 address = 0xe0 s 0 = write 0000 000 0 register address = 0x00 0 1111 00 0 address = 0xe1 s 1 = read 1 a a register 0x00 read data d7 d6 d5 d4 d2 d1 d3 d0 a register 0x02 read data d7 d6 d5 d4 d2 d1 d3 d0 a register 0x01 read data d7 d6 d5 d4 d2 d1 d3 d0 a p register 0x03 read data d7 d6 d5 d4 d2 d1 d3 d0 a p a figure 20. format for reading multiple registers input frequency (mhz) base sd clock (mhz) 12 48 13 52 19.2 48 26 52 table 5. maximum sd card clock frequency
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 31 sd port switches the sd port analog switches change states immediately whether the max14500?ax14503 are in sleep mode (wakeup = 0) or awake. if the internal usb hi-speed sd card reader is in operation, the sd card switches for the selected path are opened automatically. any writes to the sd port switch bits for that path are ignored. the sd port analog switches for the path not being used for the card reader are controllable by the host ?, and any writes to these bits affect state changes immediately. card detection the max14500?ax14503 provide an analog switch to pass the card present signal on sd card slot 1. this allows the host ? to continue using the sd slot card present switch (see figure 21). the internal analog switch can be bypassed if an alternate algorithm is used to detect card data change. the second sd card path does not provide this analog switch so if this path is used for another sd card socket, an alternate card- detection mechanism for the host ? may be needed. if the second sd card path is used for an sd interface nand chip, no card detection is required. the max14500?ax14503 do not use the sd card slot switch to detect insertion and removals. instead, a pro- tocol-based detection mechanism is used that polls for the presence or absence of an sd card. this allows both path 1 and path 2 to support an sd card slot with removable sd cards without a connection between the max14500?ax14503 and the sd socket card pre- sent switch. the pullup voltage for the card slot detec- tion may be any voltage equal to or less than v sd . enumeration the max14500?ax14503 enumerate to the usb mass storage class and appear as a usb mass stor- age device on most operating systems. usb hi-speed vs. full-speed the max14500?ax14503 support usb hi-speed and full-speed operation. the max14500?ax14503 operate at 480mbps when plugged into a hi-speed usb host, and at 12mbps when plugged into a full-speed host. usb vid/pid using i 2 c, the max14500?ax14503 have dedicated i 2 c registers for vendor identification (vid) and product identification (pid). the programmed 16-bit default val- ues are shown in the register map section. the factory default values can be replaced with your company? vid and pid. ccrd_prst mechanical card detect switch max14500?max14503 sd port1 switch ccmd1 cclk1 hcrd_prst v sd hcmd1 hclk1 cdat1_[3:0] hdat1_[3:0] host sd port card present input sd card v sd mechanical card detect switch max14500?max14503 sd port2 switch ccmd2 cclk2 hcmd2 hclk2 cdat2_[3:0] hdat2_[3:0] host sd port card present input sd card figure 21. host card detection schemes
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 32 ______________________________________________________________________________________ power-supply modes the max14500?ax14503 have four power-supply inputs (table 6). bypass v cc , v io , v sd , and v tm with high-frequency, surface-mount ceramic capacitors as close as possible to the supply pins. power-supply inputs: 1) v tm usb transceiver power. this supply powers the usb analog switches, pll subsystem, and the usb 2.0 transceiver. this regulator can be internal to a power-management ic, or it can be discrete and is recommended to be powered from usb vbus. this supply must be present when the max14500 max14503 are used in card reader mode to pass usb signals in pass thru mode. 2) v cc digital logic power. this supply powers the digital logic/internal microcontroller/flash memory. there is an internal +1.8v ldo (cldo) with shut- down controlled by the state of the mode input and internal logic. 3) v sd sd card power. this supply powers the sd card level translator and sd card switches. v sd needs to be present to pass sd signals in pass thru mode. 4) v io host interface power. this supply powers the digital i/o and i 2 c interface. power modes: 1) idle. only v io is required to be present. i 2 c registers can be updated, but no operation is possible. 2) pass thru mode. v io needs to be present so the voltage level at mode can be detected. to allow usb pass thru, the v tm supply needs to be present. to allow sd pass thru, v sd supply needs to be pre- sent. each supply is independent from the others and no power-supply sequencing is required. 3) card reader mode. all supplies are needed. when the card reader is actively transferring data, this mode draws the most current, mainly from v cc and v tm . layout considerations the max14500?ax14503 support hi-speed usb and requires careful pcb layout. use controlled-impedance matched traces of equal lengths to the usb connector with no discontinuities and a minimum number of feedthroughs. all sd traces (clk, cmd, dat_) should be of equal lengths and as short as possible. choosing pullup resistors i 2 c requires pullup resistors to provide a logic-high level to data and clock lines. there are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. every device connected to the bus introduces some capaci- tance, even when the device is not in operation. i 2 c specifies 300ns rise time to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps. to meet the rise time requirement, choose pullup resistors so the rise time (t r ) is less than 300ns where t r 0.85 x r pullup x c bus . if the transition time becomes too slow, the setup and hold times may not be met and waveforms may not be recognized. supply function range (v) v tm usb transceiver and usb switch power +2.91 to +3.4 v cc digital core 1.8v ldo +2.1 to +3.6 v sd sd card level translator and sd switches +2.0 to +3.6 v io host microprocessor level translator +1.5 to +3.6 table 6. power-supply inputs
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 33 field name read write bits reset description valid when control: control register (0x00) rfu r/w [7:5] 000 reserved for future use sd2sw r/w 4 1 setting of sd port 2 switches: 0 = open 1 = closed powered sd1sw r/w 3 1 setting of sd port 1 switches: 0 = open 1 = closed powered mode r/w [2:1] 00 activates pc usb hi-speed sd card reader: 00 = not active 01 = card reader active for sd port 1 10 = card reader active for sd port 2 11 = not active wakeup = 1 wakeup r/w 0 0 wakes the internal ?: 0 = requests ? to shut down 1 = wakes ? powered config1: configuration register 1 (0x01) sd2onebit r/w 7 0 force the sd port 2 bus to 1 bit mode: 0 = sd bus 4-bit data mode 1 = sd bus 1-bit data mode enter card reader mode sd1onebit r/w 6 0 force the sd port 1 bus to 1 bit mode: 0 = sd bus 4-bit data mode 1 = sd bus 1-bit data mode enter card reader mode intpulse r/w 5 0 int assertion method: 0 = int stays asserted until status register is read 1 = int asserts for 10ms pulse wakeup = 1 intacthi r/w 4 0 int pin active level: 0 = active-low 1 = active-high wakeup = 1 rfu r/w [3:0] 0000 reserved for future use config2: configuration register 2 (0x02) rfu r/w 7 0 reserved for future use clksource r/w [6:2] 00000 s ets the confi g ur ati on for the cl ock i np ut: 00000 = d efaul t 00001 = 19.2m h z r ai l - to- r ai l sq uar e w ave 00010 = 19.2m h z l ow - am p l i tud e ac - coup l ed si ne w ave 00101 = 13m h z r ai l - to- r ai l sq uar e w ave 00110 = 13m h z l ow - am p l i tud e ac - coup l ed si ne w ave 01001 = 12m h z r ai l - to- r ai l sq uar e w ave 01010 = 12m h z l ow - am p l i tud e ac - coup l ed si ne w ave 01101 = 26m h z r ai l - to- r ai l sq uar e w ave 01110 = 26m h z l ow - am p l i tud e ac - coup l ed si ne w ave al l other val ues = d efaul t enter card reader mode register map
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 34 ______________________________________________________________________________________ register map (continued) field name read write bits reset description valid when forcefs r/w 1 0 sets the maximum usb speed: 0 = hi-speed 1 = full speed enter card reader mode rfu r/w 0 0 reserved for future use config3: configuration register 3 (0x03) sd2maxclk r/w [7:4] 0000 limits the max clock for sd card 2. the sd clock will be the minimum of either this register or the sd card max speed register. 0111 = base sd clock/64 0110 = base sd clock/32 0101 = base sd clock/16 0100 = base sd clock/8 0011 = base sd clock/4 0010 = base sd clock/2 0001 = base sd clock 0000 = default (base sd clock) enter card reader mode sd1maxclk r/w [3:0] 0000 limits the max clock for sd card 1. the sd clock will be the minimum of either this register or the sd card max speed register. 0111 = base sd clock/64 0110 = base sd clock/32 0101 = base sd clock/16 0100 = base sd clock/8 0011 = base sd clock/4 0010 = base sd clock/2 0001 = base sd clock 0000 = default (base sd clock) enter card reader mode ie1: interrupt enable register 1 (0x04) rfu r/w 7 0 reserved for future use usbfs r/w 6 0 full-speed status change: 0 = disable contribution to int 1 = enable contribution to int powered usbsr r/w 5 0 usb suspend-resume status change: 0 = disable contribution to int 1 = enable contribution to int powered vtm r/w 4 0 v tm voltage-detector change: 0 = disable contribution to int 1 = enable contribution to int powered vsd r/w 3 0 v sd voltage-detector change: 0 = disable contribution to int 1 = enable contribution to int powered kvbus r/w 2 0 vbus voltage-detector change: 0 = disable contribution to int 1 = enable contribution to int powered
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 35 field name read write bits reset description valid when busy r/w 1 0 busy state change: 0 = disable contribution to int 1 = enable contribution to int powered sdstat r/w 0 0 sd card status change: 0 = disable contribution to int 1 = enable contribution to int note: reflects currently selected card in card reader mode powered ie2: interrupt enable register 2 (0x05) fwupd r/w 7 0 firmware update status change: 0 = disable contribution to int 1 = enable contribution to int powered rfu r/w [6:0] 0000000 reserved for future use usbvidh: usb vendor id high byte (0x06) vid 1 r/w [7:0] 0x00 bits 15? of usb vendor id reported during card reader enumeration. if this register is written, the written value is used for usb enumeration, otherwise a default vid of 0x06ba (maxim integrated products) is used. enter card reader mode usbvidl: usb vendor id low byte (0x07) vid 2 r/w [7:0] 0x00 bits 7? of usb vendor id reported during card reader enumeration. if this register is written, the written value is used for usb enumeration, otherwise a default vid of 0x06ba (maxim integrated products) is used. enter card reader mode usbpidh: usb product id high byte (0x08) pid 1 r/w [7:0] 0x00 bits 15? of usb product id reported during card reader enumeration. if this register is written, the written value is used for usb enumeration, otherwise a default pid of 0x38a4 is used. enter card reader mode usbpidl: usb product id low byte (0x09) pid 2 r/w [7:0] 0x00 bits 7? of usb product id reported during card reader enumeration. if this register is written, the written value is used for usb enumeration, otherwise if zero, a default pid of 0x38a4 is used. enter card reader mode test register (0x0a) test register r/w 0x00 do not write to this register test register (0x0b) test register r/w 0x00 do not write to this register test register (0x0c) test register r/w 0x00 do not write to this register test register (0x0d) test register r/w 0x00 do not write to this register register map (continued)
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 36 ______________________________________________________________________________________ register map (continued) field name read write bits reset description valid when test register (0x0e) test register r/w 0x00 do not write to this register fwp: firmware portal (0x0f) firmware portal r/w [7:0] 0x00 contact factory. do not write to this register. irq1: interrupt request register 1 (0x10) rfu r 7 reserved for future use usbfs r 6 0 = no change in usb full-speed mode status 1 = change in usb full-speed mode status enter card reader mode usbsr r 5 0 = no change in usb suspend/resume status 1 = change in usb suspend/resume status enter card reader mode vtm r 4 0 = no change in v tm detector status 1 = change in v tm detector status wakeup = 1 vsd r 3 0 = no change in v sd detector status 1 = change in v sd detector status wakeup = 1 vbus r 2 0 = no change in vbus detector status 1 = change in vbus detector status wakeup = 1 bsy r 1 0 = no change in busy status 1 = change in busy status wakeup = 1 sdstat r 0 0 = no change in sd card present status 1 = change in sd card present status enter card reader mode irq2: interrupt request register 2 (0x11) firmware update r 7 contact factory code download rfu r [6:0] reserved for future use status1: status register 1 (0x12) rfu r 7 reserved for future use usbfs r 6 0 = no connection or hi-speed connection 1 = full-speed connection enter card reader mode usbsr r 5 0 = usb resume 1 = usb suspend enter card reader mode vtm r 4 0 = no voltage 1 = v tm supply present wakeup = 1 vsd r 3 0 = no voltage 1 = v sd supply present wakeup = 1 vbus r 2 0 = no voltage 1 = vbus supply present wakeup = 1 bsy r 1 0 = not busy 1 = busy wakeup = 1
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 37 register map (continued) field name read write bits reset description valid when sdstat r 0 the insert/removal status is only valid for the card currently set to card reader mode (reg 0x00 bits 1-2) 0 = no card 1 = card present enter card reader mode status2: status register 2 (0x13) rfu r [7:0] reserved for future use fwugrrh: firmware upgrade response data high byte (0x14) high byte of response data r [7:0] contact factory code download fwupgrl: firmware upgrade response data low byte (0x15) low byte of response data r [7:0] contact factory code download rfu register (0x16) rfu r [7:0] reserved for future use rfu register (0x17) rfu r [7:0] reserved for future use rfu register (0x18) rfu r [7:0] reserved for future use rfu register (0x19) rfu r [7:0] reserved for future use rfu register (0x1a) rfu r [7:0] reserved for future use firmware incremental revision (0x1b) firmware incremental revision r [7:0] firmware incremental revision wakeup = 1 firmware minor revision (0x1c) firmware minor revision r [7:0] firmware minor revision wakeup = 1 firmware major revision (0x1d) firmware major revision r [7:0] firmware major revision wakeup = 1 chip revision (0x1e) chip revision r [7:0] chip revision wakeup = 1 package type (0x1f) package type r [7:0] 0x00 = 40-lead tqfn 0x05 = 56-bump wlp 0xff = unknown wakeup = 1
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 38 ______________________________________________________________________________________ cclk2 v sd v io ccmd2 cdat 2_0 hclk2 hcmd2 hdat 2_0 cdat 2_1 cdat 2_2 cdat 2_3 clk cmd dat 0 dat 1 dat 2 dat 3 hdat 2_1 hdat 2_2 hdat 2_3 clk cmd dat 0 dat 1 dat 2 dat 3 sd port2 sd interface nand flash cd+ sd port 2 switches host processor usb switches cd- d+ d- vbus hd+ hd- d+ d- usb connector sd card interface level translators 1.8v ldo vbus det microcontroller flash pll 48/52mhz sqr tcxo sram usb sie osc rom i/o level translators host interface usb 2.0 transceiver ccrd_prst cclk 1 ccmd 1 hcrd_prst hclk1 hcmd1 cdat 1_0 cdat 1_1 cdat 1_2 sd_detect clk cmd dat 0 dat 1 dat 2 hdat 1_0 hdat 1_1 hdat 1_2 sd_detect clk cmd dat 0 dat 1 dat 2 sd port1 sd slot sd card sd port 1 switches cdat 1_3 cldo v cc dat 3 hdat 1_3 mode busy berr/int usb scl sda rst add i2c_sel fref dat 3 1 f 0.1 f v sd v cc v tm (+2.91v to +3.4v) v io v io max14500?max14503 kvbus rref 1 f 0.1 f 1 f 6.19k 1% 1.5k v tm functional diagram
max14500?ax14503 hi-speed usb-to-sd card readers with bypass ______________________________________________________________________________________ 39 hcrd_prst hclk1 rref gnd v tm cd+ cd- fref gnd kvbus sda add v io busy mode rst cdat1_3 scl i2c_sel hdat1_2 hdat1_1 hdat1_0 hd- hd+ hdat1_3 cdat1_0 cdat1_1 cdat1_2 v cc cldo gnd n.c. n.c. ccmd1 ccrd_prst cclk1 hcmd1 v sd tqfn max14500 max14501 max14502 max14503 top view berr/int gnd 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 11 *ep 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 + *connect exposed pad to gnd. pin configurations
max14500?ax14503 hi-speed usb-to-sd card readers with bypass 40 ______________________________________________________________________________________ top view (bumps on bottom) max14500?max14503 cdat1_3 v io cdat1_1 876 hdat1_0 cdat1_0 cdat1_2 mode hdat1_2 hdat1_1 cd- gnd gnd fref v tm gnd hd- hd+ cd+ sda cdat2_3 hdat2_3 add v cc cdat2_2 543 n.c. n.c. hdat2_2 i2c_sel v cc hdat2_0 hdat1_3 ccmd2 kvbus cclk1 cclk2 hclk2 rref gnd hcmd2 scl v sd cldo cldo 21 gnd gnd cdat2_1 cdat2_0 ccmd1 hdat2_1 ccrd_prst hcrd_prst hclk1 hcmd1 a b c d e f g wlp busy rst berr/int pin configurations (continued) chip information process: cmos package type package code document no. 40 tqfn-ep t4055-1 21-0140 56 wlp w563b3+1 21-0090 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status.
max14500?ax14503 hi-speed usb-to-sd card readers with bypass maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 41 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/08 initial release 1 4/09 fixed data sheet to reflect new rev material including ec table , pin description , applications information , functional diagram , and pin configurations 1C41

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